As shown in FIG. 1, a typical computer system (10) has, among other components, a microprocessor (12), one or more forms of memory (14), integrated circuits (IC) (16) having specific functionalitics, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (19), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (10).
In order to properly accomplish such tasks, the computer system (10) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (18) generates a system clock signal (referred to and known in the art as “reference clock signal” and shown in FIG. 1 as SYS_CLK) to various parts of the computer system (10). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor (12) and the other components of the computer system (10) use a proper and accurate reference of time.
One component used within the computer system (10) to ensure a proper reference of time among the system clock signal and a microprocessor clock signal, i.e., “chip clock signal” or CHIP_CLK, is a type of clock generator known as a phase locked loop (PLL) (20). The PLL (20) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to the system clock signal. Referring to FIG. 1, the PLL (20) has as its input the system clock signal, which is its reference clock signal, and outputs a chip clock signal (shown in FIG. 1 as CHIP_CLK) to the microprocessor (12). The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL (20). This relationship between the phase and frequency of the system clock signal and chip clock signal ensures that the various components within the microprocessor (12) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (20), however, the operations within the computer system (10) become non-deterministic.
FIG. 2 shows a block diagram of a typical phase locked loop and buffered clock tree (200). The phase locked loop (202) receives a clock signal from clock path (201). The phase locked loop (202) outputs a clock signal on clock path (203). The clock signal on clock path (203) may have an increased frequency compared to the frequency of the clock signal on clock path (201). The phase locked loop (202) drives the clock signal on clock path (203) so that the clock signal on clock path (203) may connect to other circuits using the buffered clock tree (200).
The buffered clock tree (200) includes many buffers (230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250) to propagate and amplify the clock signal on clock path (203). The buffers (230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250) may be distributed across a microprocessor (e.g., microprocessor (12) shown in FIG. 1). The phase locked loop (202) receives an input clock signal from part of the buffered clock tree (200) formed by the clock signal on clock path (203). Accordingly, the phase locked loop (202) may adjust the timing and frequency of the clock signal on clock path (203) to compensate for some of the effects caused by the buffers (230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250).
A delay, or clock skew, on different branches of the buffered clock tree (200) may vary. Clock skew can be defined as the difference in time between an edge of a clock signal at two different locations in the integrated circuit. Furthermore, clock skew may also account for differences in edge transition rates of a signal in addition to propagation delays. The clock skew may be caused, for example, by different impedances, voltages, process variations, and temperatures. Variations in clock skew are typically accounted for in a microprocessor (e.g., microprocessor (12) shown in FIG. 1) design. As a microprocessor (e.g., microprocessor (12) shown in FIG. 1) clock frequency increases, an acceptable margin for clock skew decreases.
FIG. 3 shows an exemplary thermal profile (300) of an integrated circuit (e.g., microprocessor (12) shown in FIG. 1). The thermal profile (300) has several local hot spots (310) where more heat is generated than other locations on the integrated circuit. The hot spots (310) may have different temperatures, different sizes, different locations, and different effects on local circuits. Furthermore, the hot spots (310) may change location based on the activities of the integrated circuit. Accordingly, the clock skew of the buffers (230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250 shown in FIG. 2) in the buffered clock tree (200 shown in FIG. 2) may be affected by the temperature differences across a microprocessor (e.g., microprocessor (12) shown in FIG. 1).